Senior RTL Design Engineer

Senior RTL Design Engineer at Ixana About Ixana Ixana is a Purdue University spinoff pioneering brain-inspired wearable computing. We've developed Wi-R, a patented communication tech that's 100x more energy-efficient than Bluetooth or Wi-Fi. Join our 60-person team building the next era of real-time, AI-powered human-computer interaction. We provide comprehensive relocation support for candidates based outside Bengaluru. The Wi-R Revolution Wi-R is our patented non-radiative near-field communication technology that creates secure "wire-like wireless" experiences through small E-field bubbles around your body. This breakthrough enables unprecedented energy efficiency at sub-0.1 nanojoules per bit, making long-term wearable and implantable devices finally practical. See Wi-R in Action: High-speed data, transferred through skin contact - Demonstration of Wi-R communication What You’ll Do Micro-architect, implement, and optimize RTL for control and data path blocks in our communication SoCs. Lead digital block design efforts, working closely with system architects and analog teams. Perform RTL linting, simulation, CDC/DRC checks, and gate-level simulations. Collaborate on ECOs, MBIST/DFT integration, and low-power verification flows. Participate in RTL design reviews, power-aware simulation e.g., VCS-NLP , and multi-power domain verification using UPF. Integrate hardmacros into digital designs and ensure timing closure using STA/PNR tools. What We're Looking For Required: Bachelor's degree in Science, Engineering, or related field. One of the following must be true: You’ve been a block or chip lead for digital blocks that performed successfully in silicon, preferably in AMS-focused chips. You have a GPA ≥ 9/10 from IITs, JU, or VIT and a strong foundation in digital design. 2+ years of RTL design/verification experience 5+ years preferred . Deep knowledge of RTL Verilog/VHDL , simulation tools, linting, and CDC/DRC flows. Familiarity with ASIC ECO flows and RTL sanity tools. Experience with MBIST and DFT insertion. Strong debugging skills using simulation and waveform tools. Preferred: 5+ years of ASIC design/verification experience. Scripting skills in Tcl, Perl, or Python. Experience with DSP, wireless communication circuits, and low-power digital design. Knowledge of STA, PNR tools, and hardmacro integration workflows. Power-aware design experience using UPF and simulators like VCS-NLP. Excellent communication and documentation skills. Compensation & Benefits Base salary: Competitive and based on experience Cash bonus + meaningful early‑stage equity Relocation bonus, partner job‑search help Health insurance, paid leave, performance incentives, and employee rewards Why Join Us Work on deep tech that matters Collaborate with world-class experts and industry leaders Own your work end-to-end and see real impact Enjoy a culture of speed, rigor, and respect Competitive salary, equity, and global exposure